This invention relates to a system for interconnecting a tester of electric circuits with the circuit of a chip of a semiconductor wafer and, more particularly, to the construction of an interconnection interface with additional capacitance which serves as a source of stored energy for energizing power lines of the circuit during sudden transient demands for power during a testing of the chip circuit.
It is the practice to test the circuitry of each chip formed within a semiconductor wafer during the process of manufacturing integrated circuits. A circuit tester is used for this purpose. The tester has numerous wires for connection with the chip circuit, these wires including both signal lines and power lines. Typically, there are numerous signal lines and a few power lines. Generally, these wires are relatively large as compared to the physically small dimensions of the terminals of the chip circuit which are to be connected to the tester. Numerous test points of the circuit are to be connected to respective ones of the signal wires. Also, many circuit points of the chip circuit are to be powered with a common source of voltage so that each power line of the tester must make connection with numerous circuit points within the chip circuit.
In order to connect the wires of the tester to the terminals of the chip, various forms of interconnection systems have been devised, these systems employing an interface allowing for a fanning in of the wires from the tester to contact designated probes in a set of miniaturized probes which contact the chip terminals.
Generally, such interfaces have succeeded in establishing the desired connection between the tester wires and the chip terminals for conduction of tests of the chip circuitry. By way of example, the tests may include the application of various signals to the chip circuit and the observation of the circuit response to the test signals.
However, a problem arises in the situation wherein the test signals are administered at significantly higher frequencies and with pulse waveforms having more steeply defined leading and trailing edges than has been employed in the past. In responding to such stimuli, the chip circuit produces logic signals or other such signals having steep leading and trailing edges, which signals can be produced only by sudden changes in demand-for current from the power supply. In the usual case where a few voltages may be employed, sudden changes in demand for current appear on each of the power supply lines associated with the various voltages.
The rapid changes in demand for current are manifested on the power supply lines as high frequency signals including pulses with steep leading and trailing edges, wherein these high frequency signals carry significant amounts of power. Presently available connection interfaces are unable to provide the requisite transient response for delivering the rapid changes in current along the various power lines. Thus, instead of a sharply defined current pulse on a power line, the presently available interfaces produce a rounded current pulse. The rounded current pulse, in turn, affects the pulses produced by the chip circuit in response to the stimulus of the test signals. Consequently, the chip circuit is either unable to respond, or, alternatively, may respond with the generation of rounded signals instead of sharply defined signals.
The foregoing inadequate response of the chip circuit is detrimental for testing procedures because it tends to defeat one of the purposes of the test, namely, to determine how well the chip circuit performs. An inadequate response may be due to a malfunction within the chip circuit itself, or may be due to the failure of the power lines to deliver the rapidly changing demands for current. As a result, the presently available interfaces are suitable only for relatively low-frequency test signals rather than the higher-frequency signals necessary for operation of more modern chip circuits.